1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device comprising a plurality of external connection terminals.
2. Description of Related Art
In a related semiconductor device, transmission lines connecting between a plurality of input/output pads and a plurality of input buffers corresponding to the input/output pads are formed so as to have the same length in order to make delay times of those transmission lines equal to each other (Patent Literature 1).
Furthermore, in another related integrated memory, a delay circuit for adjusting an internal signal delay time difference is inserted between an address input terminal and an address latch circuit (Patent Literature 2).
Moreover, there has been known a related semiconductor device in which a plurality of chips are stacked so that signal transmission between the stacked chips is performed via electrodes extending through the chips (Patent Literature 3). Some of those semiconductor devices are configured such that penetrating wires have the same length (Patent Literature 4).
Patent Literature 1: JP-A 11-274414 (FIG. 2 in particular)
Patent Literature 2: JP-A 02-044597 (FIG. 1 in particular)
Patent Literature 3: JP-A 2010-182368 (FIG. 1 in particular)
Patent Literature 4: JP-A 2011-029535 (FIG. 1 in particular)